Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Spread Spectrum Clocking
Preliminary Data Sheet
Care must be taken if using a spread spectrum clock generator (SSCG) with the PPC405EZ. This controller uses a
PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is called tracking
skew. The PLL bandwidth and phase angle determine how much tracking skew exists between the SSCG and the
PLL for a given frequency deviation and modulation frequency. If using an SSCG with the PPC405EZ the following
conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC405EZ with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
• The maximum frequency deviation must not exceed −3%, and the modulation frequency must not exceed
40kHz. In some cases, on-board PPC405EZ peripherals impose more stringent requirements (see Note 1).
• Use the peripheral bus clock for logic that is synchronous to the peripheral bus because this clock tracks the
modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur, assuming that the connected device is
running at precise baud rates. If an external serial clock is used, baud rate is unaffected by the modulation.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Caution: The system designer must ensure that any SSCG used with the PPC405EZ meets these requirements
and does not adversely affect other aspects of the system.
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