Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
Table 15. I/O Specifications—All CPU Speeds (Sheet 1 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected.
2. For all interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
3. Maximum skew between IIC output signals is 6ns.
4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between
channels.
5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew
between channels.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
(TIS min)
(TIH min)
Ethernet Interface
EMCRxD[0:3]
EMCTxD[0:3]
EMCRxEr
2.5
4
19.1
19.1
na
8.7
8.7
na
EMCRxClk
EMCTxClk
EMCRxClk
20
na
na
na
2
2.5
na
4
na
4
na
na
na
EMCMDIO
EMCRxDv
19.1
na
8.7
na
async
async
2.5
na
EMCRxClk
EMCCRS
na
19.1
19.1
19.1
19.1
19.1
8.7
8.7
8.7
8.7
8.7
EMCTxEr
20
20
na
2
2
EMCTxClk
EMCTxClk
EMCTxEn
EMCMDC
na
na
na
na
na
async
async
EMCCOL
Internal Peripheral Interface
IIC0SClk
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
IIC 2.1
IIC 2.1
na
IIC 2.1
IIC 2.1
na
na
na
na
na
na
na
na
na
3
3
IIC0SData
UART0_CTS
UART0_RTS
UART0_Rx
UART0_Tx
UART1_Rx
UART1_Tx
USB_FClk
19.1
8.7
na
na
19.1
8.7
na
na
19.1
8.7
USB 2.1
USB 2.1
USB 2.1
USB 2.1
USB 2.1
USB 2.1
USB 2.1
19.1
USB 2.1
USB 2.1
USB 2.1
USB 2.1
USB 2.1
USB 2.1
USB 2.1
8.7
USB1DEV0
USB1DEV0
USB1HOST0
USB1HOST0
USB1HOST1
USB1HOST1
SPI_ClkOut
SPI_DI
4
4
4
na
na
19.1
8.7
SPI_DO
na
na
19.1
8.7
SPI_SS0:3
SPI_SS_In
CAN0_Rx
19.1
8.7
19.1
8.7
na
na
na
na
na
na
na
na
CAN0_Tx
19.1
8.7
CAN0_TxE
CAN1_Rx
19.1
8.7
na
na
CAN1_Tx
na
na
19.1
8.7
CAN1_TxE
ADC_In0:7
19.1
8.7
na
na
48
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
