Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
Power
VDD
Logic VDD supply.
na
na
na
na
na
na
na
na
na
na
na
na
OVDD1
OVDD2
GND
Non-EBC I/O VDD supply.
EBC I/O VDD supply.
System ground.
Analog Wide-
Wire receiver
ADC_AVDD
ADC_AGND
ADC analog VDD supply.
ADC analog ground.
na
na
na
na
Analog Wide-
Wire receiver
DAC analog VDD supply. It is recommended that this voltage be
provided by means of a voltage supply and voltage plane separate
from the logic voltage.
Analog Wide-
Wire receiver
DAC_AVDD
na
na
na
na
Analog Wide-
Wire receiver
DAC_AGND
PLL_AVDD
DAC analog ground.
PLL analog VDD supply. See “Absolute Maximum Ratings” on
page 41 for filter recommendations.
na
na
na
na
na
na
PLL_AGND
PLL analog ground.
Other Pins
Reserved pins. Do not make voltage, ground, or signal connections to
these pins.
Reserved
na
na
na
40
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
