Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
External Peripheral Interface
CRAM_AdV
CRAM_Clk
PerAddr04:31
BusReq
Address valid signal for PSRAM/CRAM support.
PerClk gated for PSRAM/CRAM support.
Memory address bus 4:31.
O
O
O
O
O
O
I/O
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
External PLB bus request.
PerClk
Clock output.
PerCS0:7
PerData00:31
PerOE
Chip selects 0:7.
Memory data bus 0:31.
5
Output enable.
PerReady
PerRW
Wait for PSRAM/CRAM support.
Read/Write.
O
O
O
I/O
I
PerWBE0:3
DMAAck
Write bus enable 0:3.
External DMA peripheral acknowledge.
External DMA peripheral end-of-transmission/terminal count.
External peripheral DMA request.
External request for bus access.
External request acknowledge.
External bus request priority.
DMAEOT/TC
DMAReq
5
5
HoldReq
I
HoldAck
O
I
HoldPri
NAND Flash Interface
NFALE
Address latch enable.
Cchip selects 0:3.
Command latch enable.
Data bits 0:7
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
NFCE0:3
NFCLE
O
NFData0:7
I/O
Read/Busy. If low, indicates that Read/Erase command is in process.
If high, indicates that the command is complete.
NFRB
I
3.3V LVTTL
NFRE
NFWE
Read enable.
Write enable.
O
O
3.3V LVTTL
3.3V LVTTL
Serial Peripheral Interface
SPI_ClkOut
SPI_DI
Serial peripheral interface clock.
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Master and slave input.
5
SPI_DO
Master and slave output.
O
O
I
SPI_SS0:3
SPI_SS_In
Slave Select 0:3.
Slave Select Input for multi-master collision detection.
38
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
