Revision 1.27 - August 22, 2007
PPC405EZ – PowerPC 405EZ Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
System Interface
SysClk
Description
I/O
Type
Notes
System input clock.
I
3.3V LVTTL
3.3V LVTTL
SysErr
Machine check exception has occurred.
O
Main system reset. This signal may be driven by the PPC405EZ to
cause a board level reset to occur.
SysReset
I
3.3V LVTTL
TestEn
Test enable. Reserved for manufacturing LSSD test.
Debug enable.
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5
5
4
DebugEn
Halt
I
External request to stop the processor.
Processor timer external input.
I
TmrClk
I
GPIO000:03
GPIO004:05
GPIO006:08
GPIO009
GPIO010:11
GPIO012:19
GPIO019:27
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
4
5
General purpose I/O. All of the GPIO signals are multiplexed with
other signals. Which signal a pin is connected to depends on the
setting of bits in the GPIO registers.
GPIO028:31
GPIO100:12
I/O
3.3V LVTTL
5
5
GPIO113:14
GPIO115:21
Trace Interface
TrcClk
I/O
I/O
3.3V LVTTL
3.3V LVTTL
Trace interface clock. Operates at half the CPU core frequency.
Even trace execution status.
I
I
3.3V LVTTL
3.3V LVTTL
TS1E
TS2E
TS1O
TS2O
Odd trace execution status.
Trace status.
I
I
3.3V LVTTL
3.3V LVTTL
TS3:6
Chameleon Timer Interface
PWM_DivClk
PWM_OE0
PWM_OE1:3
PWM_TBA
PWM_1:15
Divided-down clock.
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
PWM 0 Output enable input.
PWM 1:3 Output enable input.
Time Base A.
4
5
I
I/O
I/O
PWM Interface bus.
36
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
