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PPC405CR-3BC200CZ 参数 Datasheet PDF下载

PPC405CR-3BC200CZ图片预览
型号: PPC405CR-3BC200CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 405CR的PowerPC嵌入式处理器 [PowerPC 405CR Embedded Processor]
分类和应用: PC
文件页数/大小: 42 页 / 820 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.02 – January 11, 2005  
PPC405CR – PowerPC 405CR Embedded Processor  
Address Map Support  
Data Sheet  
The PPC405CR incorporates two simple and separate address maps. The first address map defines the possible  
use of address regions that the processor can access. The second address map is for Device Configuration Regis-  
ters (DCRs). The DCRs are accessed by software running on the PPC405CR processor through the use of mtdcr  
and mfdcr instructions.  
Table 1. System Memory Address Map (4GB System Memory)  
Function  
Subfunction  
Start Address  
End Address  
Size  
SDRAM and External Peripherals  
0x00000000  
0xEF5FFFFF  
3830MB  
Note: Any of the address ranges listed at  
right may be use for any of the above  
functions.  
General Use  
0xF0000000  
0xFFFFFFFF  
256MB  
Peripheral Bus Boot 1  
UART0  
Boot-up  
0xFFE00000  
0xEF600300  
0xEF600400  
0xEF600500  
0xEF600600  
0xEF600700  
0xFFFFFFFF  
0xEF600307  
0xEF600407  
0xEF60051F  
0xEF60063F  
0xEF60077F  
2MB  
8B  
UART1  
8B  
Internal Peripherals  
Notes:  
IIC0  
32B  
64B  
128B  
OPB Arbiter  
GPIO Controller Registers  
1. When peripheral bus boot is selected, Peripheral bank 0 is automatically configured at reset to the address range listed above.  
2. After the boot process, software may reassign the boot memory region for other uses.  
3. All address ranges not listed above are reserved.  
Table 2. DCR Address Map  
Function  
Total DCR Address Space1  
Start Address  
End Address  
Size  
1KW (4KB)1  
0x000  
0x3FF  
Reserved  
0x000  
0x010  
0x012  
0x014  
0x016  
0x080  
0x090  
0x0A0  
0x0A8  
0x0B0  
0x0B8  
0x0C0  
0x0D0  
0x100  
0x140  
0x00F  
0x011  
0x013  
0x015  
0x07F  
0x08F  
0x09F  
0x0A7  
0x0AF  
0x0B7  
0x0BF  
0x0CF  
0x0FF  
0x13F  
0x3FF  
16W  
2W  
Memory Controller Registers  
External Bus Controller Registers  
Decompression Controller Registers  
Reserved  
2W  
2W  
106W  
16W  
16W  
8W  
PLB Registers  
Reserved  
OPB Bridge Out Registers  
Reserved  
8W  
Clock, Control, and Reset  
Power Management  
Interrupt Controller  
Reserved  
8W  
8W  
16W  
48W  
64W  
704W  
DMA Controller Registers  
Reserved  
Notes:  
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit  
(word) register, or 1 kiloword (KW) (which equals 4 KB).  
6
AMCC  
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