Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Figure 1. PPC405CR Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
MMU
PPC405
Processor Core
GPIO
IIC
UART
UART
DCR Bus
Trace
ICU
JTAG
DCU
16KB
I-Cache
8KB
D-Cache
On-chip Peripheral Bus (OPB)
Arb
DMA
OPB
Bridge
Controller
(4-Channel)
Arb
Processor Local Bus (PLB)
Code
Decompression
(CodePack™)
External
Bus
Controller
External
SDRAM
Controller
Bus Master
Controller
13-bit addr
32-bit data
32-bit addr
32-bit data
®
The PPC405CR is designed using the IBM Microelectronics Blue Logic methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
™
way to create complex ASICs using IBM CoreConnect Bus Architecture.
AMCC
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
