Revision 2.03 – September 7, 2007
405GP – Power PC 405GP Embedded Processor
Data Sheet
Signal Functional Description (Part 4 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
Peripheral chip select bank 0.
I/O
Type
Notes
5V tolerant
3.3V LVTTL
PerCS0
O
7
Seven additional peripheral chip selects
or
General Purpose I/O. To access this function, software must toggle a
DCR bit.
5V tolerant
PerCS1:7[GPIO10:16]
PerOE
O[I/O]
O
1, 7
7
3.3V LVTTL
Used by either the peripheral controller or the DMA controller
depending upon the type of transfer involved. When the PPC405GP
is the bus master, it enables the selected device to drive the bus.
5V tolerant
3.3V LVTTL
Used by the PPC405GP when not in external master mode, as output
by either the peripheral controller or DMA controller depending upon
the type of transfer involved. High indicates a read from memory, low
indicates a write to memory.
5V tolerant
3.3V LVTTL
PerR/W
I/O
1
Otherwise it used by the external master as an input to indicate the
direction of data transfer.
5V tolerant
PerReady
PerBLast
Used by a peripheral slave to indicate it is ready to transfer data.
I
1
3.3V LVTTL
Used by the PPC405GP when not in external master mode,
otherwise used by external master. Indicates the last transfer of a
memory access.
5V tolerant
3.3V LVTTL
I/O
1, 7
DMAReq0:3 are used by slave peripherals to indicate they are
prepared to transfer data.
5V tolerant
DMAReq0:3
DMAAck0:3
I
1
6
1
3.3V LVTTL
DMAAck0:3 are used by the PPC405GP to cause the DMA
peripheral to transfer data.
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
38
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
