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PPC405GP-3DE266CZ 参数 Datasheet PDF下载

PPC405GP-3DE266CZ图片预览
型号: PPC405GP-3DE266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 405GP嵌入式处理器 [Power PC 405GP Embedded Processor]
分类和应用: PC
文件页数/大小: 59 页 / 1340 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 2.03 – September 7, 2007  
405GP – Power PC 405GP Embedded Processor  
Data Sheet  
Signal Functional Description (Part 2 of 8)  
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.  
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Bus Control Signals” on page 34.  
Signal Name  
Description  
Gnt0 when internal arbiter is used  
I/O  
Type  
Notes  
5V tolerant  
3.3V PCI  
PCIGnt0[Req]  
or  
O
Req when external arbiter is used.  
5V tolerant  
3.3V PCI  
PCIGnt1:5  
Ethernet Interface  
PHYRxD3:0  
Used as PCIGnt1:5 output when internal arbiter is used.  
O
Received data. This is a nibble wide bus from the PHY. The data is  
synchronous with the PHYRxClk.  
5V tolerant  
3.3V LVTTL  
I
O
I
1
6
1
1
Transmit data. A nibble wide data bus towards the net. The data is  
synchronous to the PHYTxClk.  
5V tolerant  
3.3V LVTTL  
EMCTxD3:0  
PHYRxErr  
PHYRxClk  
Receive Error. This signal comes from the PHY and is synchronous  
to the PHYRxClk.  
5V tolerant  
3.3V LVTTL  
5V tolerant  
3.3V LVTTL  
Receiver Medium clock. This signal is generated by the PHY.  
I
Receive Data Valid. Data on the Data Bus is valid when this signal is  
activated. Deassertion of this signal indicates end of the frame  
reception.  
5V tolerant  
PHYRxDV  
PHYCrS  
I
I
1
1
6
3.3V LVTTL  
5V tolerant  
3.3V LVTTL  
Carrier Sense signal from the PHY. This is an asynchronous signal.  
Transmit Error. This signal is generated by the Ethernet controller, is  
connected to the PHY and is synchronous with the PHYTxClk. It  
informs the PHY that an error was detected.  
5V tolerant  
3.3V LVTTL  
EMCTxErr  
O
Transmit Enable. This signal is driven by the EMAC to the PHY. Data  
is valid during the active state of this signal. Deassertion of this signal  
indicates end of frame transmission. This signal is synchronous to  
the PHYTxClk.  
5V tolerant  
3.3V LVTTL  
EMCTxEn  
O
6
5V tolerant  
PHYTxClk  
PHYCol  
This clock comes from the PHY and is the Medium Transmit clock.  
Collision signal from the PHY. This is an asynchronous signal.  
I
I
1
1
3.3V LVTTL  
5V tolerant  
3.3V LVTTL  
Management Data Clock. The MDClk is sourced to the PHY. This  
clock has a period of 400ns, adjustable via EMAC0_STACR[OPBC].  
Management information is transferred synchronously with respect to  
this clock.  
5V tolerant  
3.3V LVTTL  
EMCMDClk  
O
Management Data Input/Output is a bidirectional signal between the  
Ethernet controller and the PHY. It is used to transfer control and  
status information.  
5V tolerant  
3.3V LVTTL  
EMCMDIO[PHYMDIO]  
I/O  
1
36  
AMCC  
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