Revision 2.03 – September 7, 2007
405GP – Power PC 405GP Embedded Processor
Data Sheet
Signal Functional Description (Part 7 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
I/O
Type
Notes
General Purpose I/O
or
Even Trace execution status. To access this function, software must
toggle a DCR bit.
GPIO1[TS1E]
GPIO2[TS2E]
5V tolerant
3.3V LVTTL
I/O[O]
1, 6
General Purpose I/O
or
Odd Trace execution status. To access this function, software must
toggle a DCR bit.
5V tolerant
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5:8[TS3:6]
I/O[O]
I/O[O]
I/O[O]
1
1, 6
1
3.3V LVTTL
General Purpose I/O
or
Odd Trace execution status. To access this function, software must
toggle a DCR bit.
5V tolerant
3.3V LVTTL
General Purpose I/O
or
Trace status. To access this function, software must toggle a DCR
bit.
5V tolerant
3.3V LVTTL
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the CPU
core frequency. To access this function, software must toggle a DCR
bit.
5V tolerant
3.3V LVTTL
GPIO9[TrcClk]
I/O[O]
1
Test Enable. Used only for manufacturing tests. Pull down for normal
operation.
2.5V CMOS
w/pull-down
TestEn
RcvrInh
I
I
I
I
Receiver Inhibit. Used only for manufacturing tests. Pull up for normal
operation.
5V tolerant
3.3V LVTTL
2
2
1
Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up for
normal operation.
5V tolerant
3.3V LVTTL
DrvrInh1:2
An external clock input that can be used to clock the timers in the
CPU core.
5V tolerant
3.3V LVTTL
TmrClk
Trace Interface
Even Trace execution status. To access this function, software must
toggle a DCR bit
or
[TS1E]GPIO1
[TS2E]GPIO2
5V tolerant
O[I/O]
O[I/O]
O[I/O]
1, 6
1
3.3V LVTTL
General Purpose I/O.
Odd Trace execution status. To access this function, software must
toggle a DCR bit
or
5V tolerant
3.3V LVTTL
[TS1O]GPIO3
[TS2O]GPIO4
General Purpose I/O.
Odd Trace execution status. To access this function, software must
toggle a DCR bit
or
5V tolerant
3.3V LVTTL
1, 6
General Purpose I/O.
AMCC
41