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PPC405GP-3DE266CZ 参数 Datasheet PDF下载

PPC405GP-3DE266CZ图片预览
型号: PPC405GP-3DE266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 405GP嵌入式处理器 [Power PC 405GP Embedded Processor]
分类和应用: PC
文件页数/大小: 59 页 / 1340 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 2.03 – September 7, 2007  
405GP – Power PC 405GP Embedded Processor  
Data Sheet  
Signal Functional Description (Part 1 of 8)  
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.  
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Bus Control Signals” on page 34.  
Signal Name  
Description  
I/O  
Type  
Notes  
PCI Interface  
5V tolerant  
3.3V PCI  
PCIAD31:0  
PCI Address/Data Bus. Multiplexed address and data bus.  
PCI bus command and byte enables.  
I/O  
I/O  
5V tolerant  
3.3V PCI  
PCIC3:0[BE3:0]  
PCI parity. Parity is even across PCIAD0:31 and PCIC0:3[BE0:3].  
PCIParity is valid one cycle after either an address or data phase.  
The PCI device that drove PCIAD0:31 is responsible for driving  
PCIParity on the next PCI bus clock.  
5V tolerant  
3.3V PCI  
PCIParity  
I/O  
PCIFrame is driven by the current PCI bus master to indicate the  
beginning and duration of a PCI access.  
5V tolerant  
3.3V PCI  
PCIFrame  
PCIIRDY  
PCITRDY  
I/O  
I/O  
I/O  
2
2
2
PCIIRDY is driven by the current PCI bus master. Assertion of  
PCIIRDY indicates that the PCI initiator is ready to transfer data.  
5V tolerant  
3.3V PCI  
The target of the current PCI transaction drives PCITRDY. Assertion  
of PCITRDY indicates that the PCI target is ready to transfer data.  
5V tolerant  
3.3V PCI  
The target of the current PCI transaction can assert PCIStop to  
indicate to the requesting PCI master that it wants to end the current  
transaction.  
5V tolerant  
3.3V PCI  
PCIStop  
I/O  
I/O  
2
2
PCIDevSel is driven by the target of the current PCI transaction. A  
PCI target asserts PCIDevSel when it has decoded an address and  
command encoding and claims the transaction.  
5V tolerant  
3.3V PCI  
PCIDevSel  
PCIIDSel is used during configuration cycles to select the PCI slave  
interface for configuration.  
5V tolerant  
3.3V PCI  
PCIIDSel  
PCISErr  
I
PCISErr is used for reporting address parity errors or catastrophic  
failures detected by a PCI target.  
5V tolerant  
3.3V PCI  
I/O  
2
2
PCIPErr is used for reporting data parity errors on PCI transactions.  
PCIPErr is driven active by the device receiving PCIAD0:31,  
PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the data in  
which bad parity is detected.  
5V tolerant  
3.3V PCI  
PCIPErr  
I/O  
PCIClk is used as the asynchronous PCI clock when in  
asynchronous mode. It is unused when the PCI interface is operated  
synchronously with the PLB bus.  
5V tolerant  
3.3V PCI  
PCIClk  
I
5V tolerant  
3.3V PCI  
PCIReset  
PCI specific reset.  
O
PCI interrupt. Open-drain output (two states; 0 or open circuit)  
or  
Peripheral write enable. Low when any of the four PerWBE0:3 write  
byte enables are low.  
5V tolerant  
3.3V PCI  
PCIINT[PerWE]  
O
Multipurpose signal, used as PCIReq0 when internal arbiter is used,  
and as Gnt when external arbiter is used.  
5V tolerant  
3.3V PCI  
PCIReq0[Gnt]  
PCIReq1:5  
I
I
5V tolerant  
3.3V PCI  
Used as PCIReq1:5 input when internal arbiter is used.  
AMCC  
35  
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