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PPC405GP-3DE266CZ 参数 Datasheet PDF下载

PPC405GP-3DE266CZ图片预览
型号: PPC405GP-3DE266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 405GP嵌入式处理器 [Power PC 405GP Embedded Processor]
分类和应用: PC
文件页数/大小: 59 页 / 1340 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 2.03 – September 7, 2007  
405GP – Power PC 405GP Embedded Processor  
Data Sheet  
Signal Functional Description (Part 8 of 8)  
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.  
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Bus Control Signals” on page 34.  
Signal Name  
Description  
I/O  
Type  
Notes  
Trace status. To access this function, software must toggle a DCR bit  
or  
General Purpose I/O.  
5V tolerant  
3.3V LVTTL  
[TS3:6]GPIO5:8  
O[I/O]  
1
Trace interface clock. A toggling signal that is always half of the CPU  
core frequency. To access this function, software must toggle a DCR  
bit  
or  
5V tolerant  
3.3V LVTTL  
[TrcClk]GPIO9  
O[I/O]  
1
General Purpose I/O.  
Ground pins  
Ground  
Note: On the 456-ball packages, L11-L16, M11-M16, N11-N16, P11-  
GND  
P16, R11-R16, and T11-T16 are also thermal balls.  
On the 413-ball package, J11, J13, K11-K13, L11-L13, M11-  
N13, N11-N13, P11-P13, R11, and R13 are also thermal balls.  
OVDD pins  
OVDD  
Output driver voltage—3.3V.  
Logic voltage—2.5V.  
VDD pins  
VDD  
Other pins  
Reserved—Except for Y5 (on the 413-ball package) or AF4, do not  
connect signals, voltage, or ground to these pins. Y5 (on the 413-ball  
package) and AF4 must be tied to OVDD or GND.  
Reserved  
42  
AMCC  
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