Revision 1.10 - July 10, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 9. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut0
T
SA
Addr/Cmd
T
DS
T
HA
T
DS
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
= Setup time for address and command signals to MemClkOut0
= Hold time for address and command signals from MemClkOut0
SA
T
HA
SD
HD
T
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
T
T
DS
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 24. I/O Timing—DDR SDRAM T
DS
Notes:
1. All of the DQS signals are referenced to MemClkOut0 with the DQS delay line programmed to 1 cycle.
2. Clock speed is 200MHz.
TDS (ns)
Signal Name
Minimum
Maximum
DQS0
DQS1
DQS2
DQS3
DQS4
4
4
4
4
4
6
6
6
6
6
64
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