Revision 1.10 - July 10, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 22. DDR SDRAM Output Driver Specifications
Output Current (mA)
Signal Path
I/O H (maximum)
I/O L (maximum)
Write Data
MemData00:31
ECC0:7
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
DM0:4
MemClkOut0
MemAddr00:14
BA0:2
RAS
CAS
WE
BankSel0:1
MemClkEn
DQS0:4
MemODT0:1
DDR SDRAM Write Operation
The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes as indicated in Figure 9.
DQS rising and falling edges are centered on valid data for writes.
The data in Table 23 is generated by means of simulation and includes logic, driver, package RLC, and lengths.
Values are calculated over best case and worst case processes with speed, junction temperature, and voltage as
follows:
Table 23. DDR SDRAM Write Operation Conditions
Case
Best
Process Speed
Fast
Junction Temperature (°C)
Voltage (V)
+1.3
−40
Worst
Slow
+125
+1.1
Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and
maximum values are measured under worst case conditions. The timing numbers in the following sections are
obtained using a simulation that assumes a model as shown in Figure 8.
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