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PPC405EXR-NSC533T 参数 Datasheet PDF下载

PPC405EXR-NSC533T图片预览
型号: PPC405EXR-NSC533T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA388, 27 X 27 MM, ROHS COMPLIANT, PLASTIC, MS-034C, EBGA-388]
分类和应用: 时钟外围集成电路
文件页数/大小: 76 页 / 1105 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.10 - July 10, 2008  
PPC405EXr – PowerPC 405EXr Embedded Processor  
Preliminary Data Sheet  
Figure 10. DDR SDRAM Read Data Path for a Single Data Bit  
FF: Flip-Flop  
DDR 1X Clock  
Ext FeedBack  
Signals  
Driver  
MemFBD  
FeedBack  
Signal Gen  
Coarse Delay  
CAS Lat Delay  
Read Start  
DDR 1X Clock  
Rec  
Read Latency adjust circuit  
Stage 2 Store  
Oversampling  
Fine Delay  
MemFBR  
Fine Delay  
(Guard Band)  
DQS aligned  
feedback signal  
Cycles  
Delay  
+1  
Feedback  
T1 T2 T3 T4  
On-time sample clock  
Data Capture  
Window  
Adjust  
Oversampling  
Clock  
0
1
2
Q2_Ovs  
3
Package  
pins  
0
2
FF  
Q3  
Compare  
FF  
Q2  
PLB bus  
FF  
(x64+ECC)  
D
Read FIFO  
[0:63]  
Mux  
C
Mux  
Upper  
DQS Rising  
Edge Sync  
MemData  
Stage 2  
Stage 3  
Stage 1  
Lower  
(x32 bits +  
x8 bits ECC)  
FF  
FF  
Q3  
1
3
Q2  
(x64+ECC)  
PLB bus  
FF  
D
[64:127]  
Mux  
C
Mux  
Programmed  
Read DQS  
Delay  
DQS Falling  
Edge Sync  
DQS  
(x4 + x1  
ECC bits)  
DDR 1X Clock  
PLB 1X Clock  
ECC detection and correction if enabled occurs after Stage 3 before completing the read on the PLB.  
DDR SDRAM Read Cycle Timing  
The following diagram illustrates the relationship of the signals involved with a DDR read operation.  
AMCC Proprietary  
67  
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