Revision 1.10 - July 10, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Figure 6. Input Setup and Hold Timing Waveform for RGMII Signals
GMCnRxClk
1.25V
T
T
T
IS
T
IH
IH
IS
MIN
MIN
MIN
MIN
Inputs
1.25V
Valid
Valid
RGMII 1000Mbps timing is with reference to the raising and falling edge of GMCnRxClk.
RGMII 10/100Mbps timing is with reference only to the raising edge of GMCnRxClk.
Figure 7. Output Delay and Hold Timing Waveform for RGMII Signals
GMCnTxClk
1.25V
T
T
OH
OH
MIN
MIN
T
OV
T
OV
Outputs
MAX
MAX
High (Drive)
Float (High-Z)
Low (Drive)
Valid
Valid
Valid
Valid
RGMII 1000Mbps timing is with reference to the raising and falling edge of GMCnTxClk.
RGMII 10/100Mbps timing is with reference only to the raising edge of GMCnTxClk.
AMCC Proprietary
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