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IBM25NPE405L-3FA200CZ 参数 Datasheet PDF下载

IBM25NPE405L-3FA200CZ图片预览
型号: IBM25NPE405L-3FA200CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerNP [PowerNP]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 54 页 / 941 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Preliminary  
PowerNP NPe405L Embedded Processor Data Sheet  
Signal Functional Description (Part 4 of 6)  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.  
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.  
Signal Name  
Description  
I/O  
Type  
Notes  
DMA request. Used by peripherals to request a data  
transfer. Following a system reset, the default mode of the  
signals is active-low. They may be programmed to active-  
high using the DMA0_POL register.  
5V tolerant  
3.3V LVTTL  
[DMAReq0:3]  
I
1
DMA acknowledge. Used to indicate to peripherals that  
data transfer is complete. Following a system reset, the  
default mode of the signals is active-low. They may be  
programmed to active-high using the DMA0_POL register.  
5V tolerant  
3.3V LVTTL  
[DMAAck0:3]  
O
End Of Transfer/Terminal Count. Indication by peripherals  
that all data has been transfered, or by DMA controller that  
programmed amount of data has been transfered.  
Following a system reset, the default mode of the signals is  
active-low. They may be programmed to active-high using  
the DMA0_POL register.  
5V tolerant  
3.3V LVTTL  
[EOT0:3/TC0:3]  
I/O  
1
Internal Peripheral Interface  
Serial Clock used to provide an alternative clock to the  
internally generated serial clock. Used in cases where the  
allowable internally generated baud rates are not  
satisfactory. This input can be individually connected to  
either or both UART0 and UART1.  
5V tolerant  
3.3V LVTTL  
UARTSerClk  
I
1
1
5V tolerant  
3.3V LVTTL  
UART0_Rx  
UART0_Tx  
UART0 Receive data.  
I
O
I
5V tolerant  
3.3V LVTTL  
UART0 Transmit data.  
5V tolerant  
3.3V LVTTL  
[UART0_DCD]  
[UART0_DSR]  
[UART0_CTS]  
[UART0_DTR]  
[UART0_RTS]  
[UART0_RI]  
UART0 Data Carrier Detect.  
UART0 Data Set Ready.  
UART0 Clear To Send.  
UART0 Data Terminal Ready.  
UART0 Request To Send.  
UART0 Ring Indicator.  
1
1
1
5V tolerant  
3.3V LVTTL  
I
5V tolerant  
3.3V LVTTL  
I
5V tolerant  
3.3V LVTTL  
O
O
I
5V tolerant  
3.3V LVTTL  
5V tolerant  
3.3V LVTTL r  
1
35  
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