Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description (Part 1 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.
Signal Name
Description
I/O
Type
Notes
HDLCEX Interface
HDLCEXTxClk
HDLCEXTxFS
Transmit Clock
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Transmit Frame Synchronization
Transmit Data port A
HDLCEXTxDataA
HDLCEXTxDataB
HDLCEXRxClk
HDLCEXRxFS
O
O
I
Transmit Data port B
Receive Clock
Receive Frame Synchronization
Receive Data port A
I
HDLCEXRxDataA
HDLCEXRxDataB
I
Receive Data port B
I
5V tolerant
3.3V LVTTL
[HDLCEXTxEnA]
[HDLCEXTxEnB]
Transmit Enable port A
Transmit Enable port B
O
O
5V tolerant
3.3V LVTTL
Ethernet Interface
Management Data Clock. The MDClk is sourced to the
PHY. Management information is transferred
synchronously with respect to this clock (MII, RMII, and
SMII).
EMC0MDClk
EMC0MDIO
O
I/O
O
3.3V LVTTL
Management Data Input/Output is a bidirectional signal
between the Ethernet controller and the PHY. It is used to
transfer control and status information (MII, RMII, and
SMII).
5V tolerant
3.3V LVTTL
1, 4
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D]
EMC0TxD1[EMC0Tx0D1][EMC0Tx1D]
EMC0TxD2[EMC0Tx1D0]
Transmit Data. A nibble wide data bus towards the net.
The data is synchronous with PHY0TxClk
(MII 0[RMII 0, 1][SMII 0, 1]).
3.3V LVTTL
3.3V LVTTL
EMC0TxD3[EMC0Tx1D1]
Transmit Enable. This signal is driven by EMAC2 to the
PHY. Data is valid during the active state of this signal.
Deassertion of this signal indicates end of frame
transmission. This signal is synchronous with PHYTxClk
(MII 0[RMII 0]).
EMC0TxEn[EMC0Tx0En][EMC0Sync]
O
O
or
SMII Sync.
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous
with the PHY0TxClk. It informs the PHY that an error was
detected (MII 0).
EMC0TxErr[EMC0Tx1En]
3.3V LVTTL
or
Transmit Enable [RMII 1].
32
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
