Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description (Part 2 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.
Signal Name
Description
I/O
Type
Notes
Collision [receive error] signal from the PHY. This is an
asynchronous signal (MII 0).
5V tolerant
3.3V LVTTL
PHY0Col[PHY0Rx1Er]l
I
or
Receive Error ([RMII 1]).
Carrier Sense signal from the PHY. This is an
asynchronous signal (MII 0).
5V tolerant
3.3V LVTTL
PHY0CrS[PHY0CrS0DV]
PHY0RxClk
I
1, 5
or
Carrier sense data valid ([RMII 0]).
Receiver medium clock. This signal is generated by the
PHY (MII 0).
5V tolerant
3.3V LVTTL
I
I
1, 4
1, 4
PHY0RxD0[PHY0Rx0D0][PHY0Rx0D]
PHY0RxD1[PHY0Rx0D1][PHY0Rx1D]
PHY0RxD2[PHY0Rx1D0]
Received Data. This is a nibble wide bus from the PHY.
The data is synchronous with PHY0RxClk
(MII 0[RMII 0, 1][SMII 0, 1]).
5V tolerant
3.3V LVTTL
PHY0RxD3[PHY0Rx1D1]
Receive Data Valid. Data on the Data Bus is valid when
this signal is activated. Deassertion of this signal indicates
end of the frame reception (MII 0).
5V tolerant
3.3V LVTTL
PHY0RxDV[PHY0CrS1DV]
PHY0RxErr[PHY0Rx0Er]
I
1, 5
or
Carrier sense data valid ([RMII 1])
Receive Error. This signal comes from the PHY and is
synchronous with PHY0RxClk (MII 0 [RMII 0]).
5V tolerant
3.3V LVTTL
I
I
1, 5
1, 4
Transmit medium clock. This signal is generated the PHY
([MII 0]).
5V tolerant
PHY0TxClk[PHY0RefClk]
SDRAM Interface
or
3.3V LVTTL
Reference Clock [RMII and SMII].
Memory Data bus
Notes:
MemAddr00:31
I/O
O
3.3V LVTTL
3.3V LVTTL
1. MemAddr00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
Memory Address bus.
Notes:
MemAddr12:00
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
BA1:0
RAS
Bank Address supporting up to 4 internal banks
Row Address Strobe.
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
CAS
Column Address Strobe.
DQM for byte lane 0 (MemAddr00:7),
1 (MemAddr08:15),
DQM0:3
DQMCB
O
O
3.3V LVTTL
3.3V LVTTL
2 (MemData16:23), and
3 (MemData24:31)
DQM for ECC check bits.
33
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
