Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device.
Characteristic
Supply Voltage (Internal Logic)
Symbol
Value
Unit
V
V
0 to +2.7
0 to +3.6
0 to +2.7
DD
OV
Supply Voltage (I/O Interface)
V
DD
2
AV
V
PLL Supply Voltage
DD
V
-0.6 to (OV + 0.6)
Input Voltage (3.3V LVTTL receivers)
Input Voltage (5.0V LVTTL receivers)
Storage Temperature Range
Case temperature under bias
Notes:
V
V
IN
DD
V
-0.6 to (OV + 2.4)
IN
DD
T
-55 to +150
-40 to +120
°C
°C
STG
T
C
1. All voltages are specified with respect to ground (GND).
2. AV should be derived from V using the following circuit:
DD
DD
L1 – 2.2µH SMT inductor (equivalent to MuRata
AV
V
DD
DD
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
L1
C1 – 3.3 µF SMT tantalum
C1
C2
C3
C2 – 0.1µF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
C3 – 0.01µF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
Package Thermal Specifications
The NPe405L is designed to operate within a case temperature range of -40°C to 85°C. Thermal resistance values for the
E-PBGA packages in a convection environment are as follows:
Airflow
ft/min (m/sec)
Symbol
Package—Thermal Resistance
Unit
0 (0)
100 (0.51)
200 (1.02)
23mm, 324-balls—Junction-to-Case
θJC
θCA
2
2
2
°C/W
°C/W
1
17
15
14
23mm, 324-balls—Case-to-Ambient
Notes:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, T , is measured at top center of case surface with device soldered to circuit board.
C
b. T = T – P×θCA, where T is ambient temperature and P is power consumption.
A
C
A
c. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption.
38
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
