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IBM25NPE405L-3FA200CZ 参数 Datasheet PDF下载

IBM25NPE405L-3FA200CZ图片预览
型号: IBM25NPE405L-3FA200CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerNP [PowerNP]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 54 页 / 941 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Preliminary  
PowerNP NPe405L Embedded Processor Data Sheet  
Signal Functional Description (Part 6 of 6)  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.  
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.  
Signal Name  
Description  
I/O  
Type  
Notes  
System Interface  
3.3V Analog  
Wire w/ESD  
SysClk  
SysReset  
SysErr  
Main System Clock input.  
I
I/O  
O
I
5V tolerant  
3.3V LVTTL  
Main System Reset.  
1, 2  
5V tolerant  
3.3V LVTTL  
Set to 1 when a Machine Check is generated.  
Halt from external debugger.  
5V tolerant  
3.3V LVTTL  
Halt  
1
1
General Purpose I/O. To access this function, software  
must toggle a DCR bit.  
5V tolerant  
3.3V LVTTL  
GPIO00:31  
TestEn  
I/O  
I
Test Enable. Used only for manufacturing tests. Pull down  
for normal operation.  
3.3V LVTTL  
Rcvr w/PD  
This input must toggle at a rate of less than one half the  
CPU core frequency (less than 100MHz in most cases). In  
most cases this input toggles much slower (in the 1MHz to  
10MHz range).  
5V tolerant  
3.3V LVTTL  
TmrClk  
I
1
Trace Interface  
[TS1E]  
[TS2E]  
Even Trace execution status.To access this function,  
software must toggle a DCR bit.  
5V tolerant  
3.3V LVTTL  
O
O
O
[TS1O]  
[TS2O]  
Odd Trace execution status. To access this function,  
software must toggle a DCR bit.  
5V tolerant  
3.3V LVTTL  
Trace Status. To access this function, software must toggle  
a DCR bit.  
5V tolerant  
3.3V LVTTL  
[TS3:6]  
[TrcClk]  
Trace interface clock. A toggling signal that is always half  
of the CPU core frequency. To access this function,  
software must toggle a DCR bit.  
5V tolerant  
3.3V LVTTL  
O
1
Power Pins  
Ground  
GND  
I
Hardwire  
Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14,  
and P09-P14 are also thermal balls.  
V
Logic voltage—2.5V  
I
I
Hardwire  
Hardwire  
DD  
OV  
Output driver voltage—3.3V  
DD  
3.3V DC  
AV  
Filtered PLL voltage—2.5V  
I
DD  
Wire w/ESD  
Other Pins  
Reserved  
Do not connect signals, voltage, or ground to these pins.  
n/a  
n/a  
37  
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