Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Architectural Overview
Data Sheet
To increase data throughput, the Pass-Thru channel
incorporates two 32-byte FIFOs. One FIFO is dedi-
cated to PCI read data while the other is dedicated to
PCI write data. Enabling the write FIFO allows the
S5320 to accept zero wait state bursts from the PCI
bus regardless of the Add-On bus application design
speed. Figure 4 illustrates the Pass-Thru block.
states since data has been prefetched into the FIFO.
Either of the write/read FIFOs can be disabled or
enabled to tune system performance.
The Add-On bus can be operated in two different
modes: active or passive. The passive mode of opera-
tion mimics that of the S5335 Add-On bus operation.
The user design drives S5320 pins to read or write
data. In active mode, the Add-On bus is driven from an
S5320 internal state machine. This reduces compo-
nent count in cost-sensitive designs. Active mode also
incorporates programmable wait states from 0 to 7.
Enabling the read FIFO allows data to be optionally
prefetched from the Add-On Bus. This can greatly
improve performance of slow Add-On bus designs.
PCI read cycles can be performed with zero wait
Figure 4. Pass-Thru Block Diagram
32
Endian
Conv.
32-Byte
FIFO
Pass-Thru Register
32
PCI
Decode
Control
Add-On
Decode
Control
Status/CTRL Register
32
32
32-Byte
FIFO
Endian
Conv.
Pass-Thru Register
18
DS1656
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