Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Architectural Overview
Data Sheet
and Add-On Operation Registers. All of these registers
are user configurable through their associated buses
and from the external nvRAM. The following sections
provide a brief overview of each register group and the
nvRAM interface.
ARCHITECTURAL OVERVIEW S5320
Since the S5320 is a PCI Target or Slave device only,
its cost is significantly less than PCI Bus Master solu-
tions. The S5320 is PCI purposed 2.2 compliant and
can support data transfer rates up to 132 Mbytes/sec.
Burst transfers and single data transfers are both sup-
ported. Figure 1 shows the block diagram for the
S5320.
PCI Configuration Registers
All PCI compliant devices are required to provide a
group of PCI configuration registers. These registers
are polled by the host BIOS system during power-up
initialization. They contain specific device and product
information such as Vendor ID, Device ID, Subsystem
Vendor ID, memory requirements, etc. These registers
are located in the S5320 and are either initialized with
predefined default values or user customized defini-
tions contained in the external nvRAM.
Many additional S5320 features offer the user easier
hardware and software implementation. Up to four
memory or I/O size definable blocks, referred to as
Pass-Thru regions, are provided for multiple device
configurations. Data transfers via a Pass-Thru region
can be performed either direct to the Add-On bus or
through two 32-Byte burstable FIFOs. Added read
prefetch and programmable FIFO wait state features
allow the user to tune system performance. The Pass-
Thru data channel also supports an active/passive
mode bus interface. Passive mode requires the
designer to transfer data by externally driving the Add-
On bus. Active mode minimizes design components
by enabling internal logic to drive or acquire the Add-
On bus to read or write data independently. Active
mode provides programmable wait state generation
for slower Add-On designs.
PCI Bus Accessible Registers
The second group of registers are the PCI Operation
Registers. This group of registers is accessible to the
PCI Bus. These are the primary registers through
which the PCI Host configures the S5320 operation
and communicates with the Add-On Bus. These regis-
ters encompass the PCI bus mailboxes, Pass-Thru/
FIFO data channel and Status/ Control registers.
Add-On Bus Accessible Registers
Two 32-bit mailbox registers are implemented for addi-
tional data or user-defined status/command transfers.
Each mailbox may be examined for empty or full, at
the byte level, through a mailbox status register. Mail-
box transfers can be either register style or hardware
direct. Dedicated external mailbox data and strobe
pins are provided for direct hardware read/writes and
allow Add-On to PCI interrupt capabilities. A direct
Add-On to a PCI bus interrupt pin is incorporated, add-
ing design flexibility.
The last register group consists of the Add-On Opera-
tion Registers. This group of registers is accessible via
the Add-On Bus. These are the primary registers
through which the Add-On application configures
S5320 operation and communicates with the PCI Bus.
These registers encompass the Add-On bus mail-
boxes, Pass-Thru/FIFO Registers and Status/Control
Registers.
SERIAL NON-VOLATILE INTERFACE
The S5320 supports a two-wire serial nvRAM. This
allows the designer to customize the device configura-
tion to be loaded during power-up initialization. An
expansion BIOS may also be contained in the nvRAM.
Previously indicated, the S5320 contains the required
set of PCI Configuration Registers. These registers
can be initialized with default values or with custom-
ized values contained in an external nvRAM. The
nvRAM allows Add-On card manufacturers to initialize
the S5320 with their specific Vendor ID values, along
with other desired S5320 operation characteristics.
S5320 REGISTER ARCHITECTURE
S5320 communications, control and configuration is
performed through three primary groups of registers:
PCI Configuration Registers, PCI Operation Registers
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