Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Signal Description
PCI BUS SIGNALS
Data Sheet
The following sets of signals represent the interface pins available for the S5320 to PCI bus.
Table 1. PCI Bus Address and Data Signal
Signal
Type
Description
AD[31:0]
t/s
Address/Data. Address and data are multiplexed on the same PCI bus pins. A PCI bus transaction
consists of an address phase followed by one or more data phases. An address phase occurs on the
PCLK cycle in which FRAME# is asserted. A data phase occurs on the PCLK cycles in which IRDY#
and TRDY# are both asserted.
C/BE[3:0]#
in
Command/Byte Enable. Bus commands and byte enables are multiplexed on the same pins. These
pins define the current bus command during an address phase. During a data phase, these pins are
used as Byte Enables, with C/BE[0]# enabling byte 0 (LSB) and C/BE[3]# enabling byte 3 (MSB).
C/BE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
1000
1001
1010
1011
1100
1101
1110
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
1111
PAR
t/s
Parity. Parity is always driven as even from all AD[31:0] and C/BE[3:0]# signals. The parity is valid dur-
ing the clock following the address phase and is driven by the bus master. During a data phase for
write transactions, the bus master sources this signal on the clock following IRDY# active; during a
data phase for read transactions, this signal is driven by the target and is valid on the clock following
TRDY# active. The PAR signal has the same timing as AD[31:0], delayed by one clock.
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