Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Architectural Overview
Data Sheet
MAILBOX OPERATION
PASS-THRU OPERATION
The mailbox registers are divided into two 4-byte sets.
Each set is dedicated to one bus for data transfer to
the other bus. Figure 3 shows a block diagram of the
mailbox section of the S5320. The provision of mailbox
registers provides data or user defined command/sta-
tus transfer capability between two buses. An empty/
full indication for each mailbox register, at the byte
level, is determined by polling a status register acces-
sible to both the PCI and Add-On buses. Providing
mailbox byte level full indications allows greater flexi-
bility in 8-, 16-or 32-bit designs; i.e., transferring a
single byte in 8-bit Add-On bus without requiring the
assembly or disassembly of 32-bit data.
Pass-Thru region accesses can execute PCI bus
cycles in real time or through an internal FIFO. Real
time operation allows the PCI bus to directly read or
write to Add-On bus resources. The S5320 allows the
designer to declare up to four individual Pass-Thru
regions. Each region may be defined as 8, 16 or 32
bits wide, mapped into memory or I/O system space
and may be up to 512 MB in size. Figure 4 shows a
basic block diagram of the S5320 Pass-Thru
architecture.
Host communications to the Pass-Thru data channel
utilizes dedicated Add-On bus pins to signal that a PCI
read or write has been requested. User logic decodes
these signals to determine if it must read or write data
to the S5320 to satisfy the PCI request. Information
decoded includes: PCI read/write transaction request,
the byte lanes involved, the specific Pass-Thru region
accessed and whether the request is a burst or single
cycle access.
A mailbox byte level interrupt feature for PCI or Add-
On buses is provided. Bit locations configured within
the S5320 operation registers can select which mail-
box byte is to generate an interrupt when the mailbox
is written to. Interrupts can be generated to the PCI or
Add-On buses. PCI bus interrupts may also be gener-
ated from direct hardware interfacing due to a unique
S5320 feature. The Add-On mailbox is hardware
accessible via a set of dedicated device pins. A single
load pulse latches data into the mailbox generating an
interrupt, if enabled.
Pass-Thru operation supports single PCI data cycles
and PCI data bursts. During PCI burst operations, the
S5320 is capable of transferring data at the full PCI
bandwidth. Should slower Add-On logic be imple-
mented, the S5320 will issue a PCI bus retry until the
requested transfer is completed.
Figure 3. Mailbox Block Diagram
8
8
8
8
Mailbox Mailbox Mailbox Mailbox
Byte0 Byte1 Byte2 Byte3
32
PCI
Decode
Control
Add-On
Decode
Control
32
MailboxStatus
Register
Mailbox Mailbox Mailbox Mailbox
Byte0
Byte1
Byte2
Byte3
8
8
8
8
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
