Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Architectural Overview
Data Sheet
Figure 2. S5320 Pinout
S5320
PCLK
BPCLK
ADCLK
SYSRST#
IRQ#
INTA#
RST#
Add-OnBus
Timing/Interrupts
AD[31:0]
ADDINT#
DQ[31:0]
C/BE[3:0]#
Add-OnDataBus
SELECT#
ADR[6:1]
S5320Data
AccessControl
FRAME#
DEVSEL#
BE[3:0]#
RD#
WR#
IRDY#
TRDY#
IDSEL#
PTATN#
PTBURST#
PTNUM[1:0]
PTBE[3:0]#
STOP#
LOCK#
Pass-Thru
Control/
Access
PTADR#
PTWR
PAR
PTRDY#/WAIT#
PERR#
SERR#
DXFER#
PTMODE
DQMODE
Add-OnBus
Control
S5320
Control
FLT#
MD[7:0]
LOAD#
Mai l Box
Access/Control
MDMODE
SDA
SCL
SerialBus
Config/BIOSOpt.
16
DS1656
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