Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
ADD-ON LOCAL BUS INTERFACE
Data Sheet
The DQMODE signal configures the data path width
for all Add-On Operation register accesses, except for
the Pass-Thru Data and Address registers. When
DQMODE is low, DQ is configured as a 32-bit data
bus. When DQMODE is high, DQ is configured as a
16-bit data bus. For 16-bit operation, BE3# is rede-
fined as ADR1, providing an extra address input, and
BE2# is unused. ADR1 selects the low or high words
of the 32-bit S5320 Add-On Operation Registers.
This chapter describes the Add-On Local bus interface
of the S5320. The S5320 is designed to support con-
nection to a variety of microprocessor buses and/or
peripheral devices. The Add-On interface controls
S5320 operation through the Add-On Operation Reg-
isters accessed through the 32 bit local bus.
The Add-On local bus interface is synchronous to
ADCLK. ADCLK is a 0-40 MHz clock input which can
be configured as asynchronous to the PCI clock or
synchronous when connected to the S5320 BPCLK
output. The following sections describe the various
interfaces to the PCI bus and how they are accessed
from the Add-On bus.
ADD-ON S5320 REGISTER ACCESSES
The S5320 Add-On bus is very similar to that of a
memory or peripheral device found in a microproces-
sor-based system. A 32-bit data bus with individual
read and write strobes, a chip select and byte enables
are provided.
ADD-ON INTERFACE SIGNALS
Register Access Signals
The Add-On bus provides a number of system signals
to allow Add-On logic to monitor PCI bus activity, to
indicate status conditions (interrupts), and to configure
the S5320 Add-On bus.
Register accesses to the S5320 Add-On Operation
Registers are synchronous to the Add-On input clock
(ADCLK). The following signals are required to com-
plete a register access to the S5320.
SYSTEM SIGNALS
BE[3:0]# Byte Enable Inputs. These signals identify
which bytes of the DQ bus are valid during Add-
On bus transactions. BE0# indicates valid
DQ[7:0], BE1# a valid DQ[15:8], etc. When DQ is
configured for 16-bit operation, BE2# is not
defined and BE3# becomes ADR1.
BPCLK is a buffered version of the PCI clock. The PCI
clock can operate from 0 MHz to 33 MHz.
SYSRST# is a buffered version of the PCI reset signal,
and may also be toggled by host application software
through bit 24 of the Reset Control Register (RCR).
ADR[6:2] Address Register Inputs. These pins
address a specific Add-On Operation Register
within the S5320. When DQ is configured for 16-
bit operation, an additional input, ADR1 is avail-
able to allow the 32-bit operation registers to be
accessed in two 16-bit cycles.
IRQ# is the PCI interrupt request output to the Add-On
bus. This signal is active low and can indicate multiple
conditions. Add-On interrupts can be generated from
the mailbox interface or to indicate start of BIST. The
conditions which will generate an IRQ# due to mailbox
activity are discussed in the mailbox chapter. The
IRQ# output is deasserted when acknowledged by
writing a 1 to the corresponding interrupt bit in the
Add-On Interrupt Control/Status Register (AINT). See
Table 30.
RD# Read Enable Input.
WR# Write Enable Input.
SELECT# Chip Select Input. This input indicates RD#,
WR#, ADR[6:2] and BE[3:0] are valid.
The PTMODE signal (Pass-Thru Mode) controls the
Pass-Thru interface only. Asserting it will configure the
Pass-Thru in Passive mode and low will configure the
Pass-Thru in Active mode.
DQ[31:0] Bi-directional Data Bus. These I/O pins are
the Add-On data bus.
S5320 General Register Accesses
ADDINT# is an Add-On interrupt input pin. When
asserted, it will cause the PCI interrupt output pin
(INTA#) to assert. The ADDINT# is a level-sensitive
input. Any number of Add-On peripheral interrupt
sources can drive this input. There must be a pull-up
resistor on the board to pull it high when inactive. This
interrupt has to be enabled by Bit 13 of the INTCSR. It
is the responsibility of the PCI host to clear the inter-
rupt source of ADDINT# in order to have the pending
interrupt deasserted.
For many Add-On applications, Add-On logic does not
operate at the PCI bus frequency. This is especially
true for Add-On designs implementing a microproces-
sor, which may be operating at a lower or higher
frequency.
The RD# and WR# inputs become enables, using
ADCLK to clock data into and out of registers. All
inputs are sampled on the rising edge of ADCLK.
108
DS1656
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
