MAX 7000 Programmable Logic Device Family Data Sheet
Table 24. EPM7032S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
fACNT
fMAX
Maximum internal array clock (4)
frequency
175.4
142.9
116.3
100.0
MHz
MHz
Maximum clock frequency
(5)
250.0
200.0
166.7
125.0
Table 25. EPM7032S Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min Max Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.2
0.2
2.2
3.1
0.9
2.6
2.5
0.7
0.2
0.7
5.2
4.0
4.5
9.0
4.0
0.2
0.2
2.1
3.8
1.1
3.3
3.3
0.8
0.3
0.8
5.3
4.0
4.5
9.0
4.0
0.3
0.3
2.5
4.6
1.4
4.0
4.0
1.0
0.4
0.9
5.4
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tFIN
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
tOD2
tOD3
tZX1
tZX2
tZX3
tXZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
tSU
0.8
1.7
1.9
1.0
2.0
1.8
1.3
2.5
1.7
2.0
3.0
3.0
tH
Register hold time
tFSU
Register setup time of fast
input
tFH
Register hold time of fast
input
0.6
0.7
0.8
0.5
ns
tRD
Register delay
1.2
0.9
2.7
2.6
1.6
2.0
1.6
1.1
3.4
3.3
1.4
2.4
1.9
1.4
4.2
4.0
1.7
3.0
2.0
2.0
5.0
5.0
1.0
3.0
ns
ns
ns
ns
ns
ns
tCOMB
tIC
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
tEN
tGLOB
tPRE
Altera Corporation
37
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