MAX 7000 Programmable Logic Device Family Data Sheet
Table 23. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-15T
Min Max Min Max Min Max
Unit
-15
-20
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
2.0
2.0
–
3.0
3.0
4.0
9.0
2.0
8.0
8.0
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tFIN
(2)
(2)
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Shared expander delay
Parallel expander delay
Logic array delay
10.0
1.0
6.0
6.0
–
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
VCCIO = 5.0 V
C1 = 35 pF
4.0
tOD2
tOD3
tZX1
tZX2
tZX3
Output buffer and pad delay
Slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 35 pF
5.0
8.0
–
–
6.0
9.0
ns
ns
ns
ns
ns
Output buffer and pad delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
Output buffer enable delay
Slow slew rate = off
6.0
6.0
–
10.0
11.0
14.0
10.0
V
CCIO = 5.0 V
Output buffer enable delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 5 pF
7.0
V
CCIO = 3.3 V
Output buffer enable delay
Slow slew rate = on
10.0
6.0
–
V
CCIO = 5.0 V or 3.3 V
tXZ
Output buffer disable delay
Register setup time
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
4.0
4.0
2.0
2.0
4.0
4.0
–
4.0
5.0
4.0
3.0
tH
Register hold time
tFSU
tFH
Register setup time of fast input (2)
Register hold time of fast input (2)
Register delay
–
tRD
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
15.0
1.0
1.0
8.0
8.0
3.0
4.0
4.0
3.0
15.0
tCOMB
tIC
Combinatorial delay
Array clock delay
tEN
Register enable time
Global control delay
Register preset time
Register clear time
tGLOB
tPRE
tCLR
tPIA
tLPA
PIA delay
Low-power adder
(8)
Altera Corporation
35
ALTERA [ ALTERA CORPORATION ]
