JTAG & In-System Programmability
The Quartus II software, Jam STAPL player, and Jam Byte-Code Player
provides the designer with the option to control real-time ISP (if used)
and allows the designer to control the timeline of new design
configuration into the SRAM (immediately or upon next power cycle).
Design Security
All MAX II devices contain a programmable security bit that controls
access to the data programmed into the CFM block. When this bit is
programmed, design programming information, stored in the CFM
block, cannot be copied or retrieved. This feature provides a high level of
design security because programmed data within flash memory cells is
invisible. The security bit that controls this function, as well as all other
programmed data, is reset only when the device is erased. The SRAM is
also invisible and cannot be accessed regardless of the security bit setting.
The UFM block data is not protected by the security bit and is accessible
through JTAG or logic array connections.
Programming with External Hardware
MAX II devices can be programmed by downloading the information via
®
in-circuit testers, embedded processors, the Altera ByteblasterMV™,
MasterBlaster™, ByteBlaste™r II, and USB-Blaster cables, and through
the universal serial bus (USB)-based Altera Programming Unit (APU)
with the appropriate adapter.
BP Microsystems, System General, and other programming hardware
manufacturers provide programming support for Altera devices. Check
their web sites for device support information.
Altera Corporation
June 2004
Core Version a.b.c variable
3–9
MAX II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
