In System Programmability
UFM Programming
The Quartus II software, with the use of POF, Jam, or JBC files, supports
programming of each user flash memory (UFM) block sector
independent from the logic array design pattern stored in the CFM block.
This allows updating or reading UFM contents through ISP without
altering the current logic array design, or vice versa. By default, these
programming files and methods will program both the entire flash
memory contents, which includes the CFM block and UFM contents. The
stand-alone embedded Jam STAPL player and Jam Byte-Code Player
provides action commands for programming or reading the entire flash
memory (UFM and CFM together) or each independently.
f
For more information, see the chapter on Using Jam STAPL for ISP via an
Embedded Processor.
In-System Programming Clamp
By default, the IEEE 1532 instruction used for entering ISP automatically
tri-states all I/O pins with weak pull-up resistors for the duration of the
ISP sequence. However, some systems may require certain pins on
MAX II devices to maintain a specific DC logic level during an in-field
update. For these systems, an optional in-system programming clamp
instruction exists in MAX II circuitry to control I/O behavior during the
ISP sequence. The in-system programming clamp instruction enables the
device to sample and sustain the value on an output pin (an input pin
would remain tri-stated if sampled) or to explicitly set a logic high, logic
low, or tri-state value on any pin. Setting these options is controlled on an
individual pin basis using the Quartus II software.
Real-Time ISP
For systems that require more than DC logic level control of I/O pins, the
real-time ISP feature allows you to update the CFM block with a new
design image while the entire current design continues to operate in the
SRAM logic array and I/O pins. A new programming file is updated into
the MAX II device without halting the original design’s operation, saving
down-time costs for remote or field upgrades. The updated CFM block
configures the new design into the SRAM upon the next power cycle. It is
also possible to execute an immediate configuration of the SRAM without
a power cycle by using a specific sequence of ISP commands. The
configuration of SRAM without a power cycle takes a specific amount of
time (tCONFIG). During this time, the I/O pins are tri-stated and weakly
pulled-up to VCCIO
.
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Core Version a.b.c variable
Altera Corporation
June 2004
MAX II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
