17–16
Chapter 17: Understanding and Evaluating Power in MAX II Devices
Conclusion
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Reduce the loading and/or external capacitance on the outputs. Excessive loading
and capacitance of printed circuit board (PCB) traces and other ICs on the output
pins significantly increases the power. Keeping excess load and external
capacitance to a minimum on the outputs pins whenever possible will
significantly reduce the current necessary for the device.
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Reduce the amount of circuitry in the device. Power depends on the amount of
internal logic that switches at any given time. Reducing the amount of logic in a
device reduces the current in the device and thus reduces the power.
Modify the design to reduce power. Identify areas in the design that can be revised
to reduce the power requirements. Common solutions include reducing the
number of switching nodes and/or required logic, and removing redundant
unnecessary signals.
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Modify I/O Locations. Grouping I/O pins from common logic blocks allows the
Quartus II software to place the associated logic closer together. The more compact
a logic block and I/O, the lower its dynamic power (especially true of low
utilization designs with I/O spread around the device).
Increase the performance requirements in the constraint file. Improving the
performance that is beyond the need for operation reduces the power dissipation.
The Quartus II software optimizes the design and places logic closer together, uses
shorter routing and fewer logic levels, and lowers dynamic power and improves
performance.
f
MAX II devices offer a power-down capability that conserves battery life for portable
applications. For more information about the power-down capability in MAX II
devices and an application design example, refer to AN 422: Power Management in
Portable Systems Using MAX II CPLDs.
Conclusion
This chapter discusses how to evaluate and manage MAX II power by using the MAX
II PowerPlay Early Power Estimator spreadsheet. This power estimation tool
estimates the power consumption for your design based on typical conditions. The
MAX II board-level designer can exploit the power calculator before board design and
layout. The MAX II PowerPlay Early Power Estimator spreadsheet is available on the
Altera website at www.altera.com.
Referenced Documents
This chapter references the following documents:
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AN 422: Power Management in Portable Systems Using MAX II CPLDs
PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
