12. Real-Time ISP and ISP Clamp for MAX
II Devices
MII51019-1.6
Introduction
During in-system programming, most CPLDs automatically tri-state their
input/output (I/O) pins to prevent contention issues on a board. After successful
programming, the device enters user mode and the new design begins to function.
®
Apart from this normal programming mode, MAX II devices also support real-time
in-system programmability (ISP) and ISP Clamp programming modes, which allow
control of I/O and device behavior during ISP. This chapter describes the following
®
two features and how to use them in the Quartus II software, as well as the Jam™
Standard Test and Programming Language (STAPL) and Jam STAPL Byte-Code
Players:
■
“Real-Time ISP” on page 12–1
“ISP Clamp” on page 12–4
■
Real-Time ISP
Real-time ISP allows you to program a MAX II device while the device is still in
operation. The new design only replaces the existing design when there is a power
cycle to the device (i.e., powering down and powering up again). This feature enables
you to perform in-field updates to the MAX II device at any time without affecting the
operation of the whole system.
How Real-Time ISP Works
For normal ISP operation, downloading the new design data from the configuration
flash memory (CFM) to the SRAM begins after the completion of CFM programming.
During the process of CFM programming and subsequent downloading of CFM data
to SRAM, I/O pins will remain tri-stated. After the CFM download to the SRAM, the
device resets and enters user mode operation. Figure 12–1 shows the flow of normal
programming.
Figure 12–1. MAX II Device with Normal ISP Operation
1
1
Programming
Data
JTAG
CFM
2
SRAM
(Logic Array)
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
