Chapter 12: Real-Time ISP and ISP Clamp for MAX II Devices
12–5
ISP Clamp
With the ISP clamp feature in MAX II devices, you can hold each I/O pin of a device
to a specified static state when programming the device. You can set the state in the
Quartus II software. After successfully programming the device in ISP clamp mode,
those I/O pins will be released and function according to the new design.
This feature can be used to indicate when the device is being programmed and when
the programming is done by setting a particular pin to a specific state (different from
the state when the device is in user mode) when the device enters ISP clamp mode.
How ISP Clamp Works
When the ISP clamp feature is used, you can set the I/O pins to tri-state (default),
high, low, or even sample the existing state of a pin and hold the pin to that state
when the device is in ISP clamp operation. The software determines the values to be
scanned into the boundary-scan registers of each I/O pin, based on your settings. This
will determine the state of the pins to be clamped to when the device programming is
in progress. The weak I/O pull-up resistors are disabled during programming when
the ISP clamp feature is used, even if the I/O is clamped to a tri-state value.
Before clamping the I/O pins, the SAMPLE/PRELOAD JTAG instruction is first
executed to load the appropriate values to the boundary-scan registers. After loading
the boundary-scan registers with the appropriate values, the EXTEST instruction is
executed to clamp the I/O pins to the specific values loaded into the boundary-scan
registers during SAMPLE/PRELOAD.
If you choose to sample the existing state of a pin and hold the pin to that state when
the device enters ISP clamp mode, you must make sure that the signal is in steady
state. You need a steady state signal because you cannot control the sample set-up
time as it depends on the TCKfrequency as well as the download cable and software.
You might not capture the correct value when sampling a signal that toggles or is not
static for long periods of time. Figure 12–5 shows the ISP clamp operation.
Figure 12–5. ISP Clamp Operation
1
2
3
Before Programming
(User Mode)
During Programming
(ISP Clamp Mode)
After Programming
(User Mode)
JTAG
CFM
Programming
Data
JTAG
CFM
JTAG
CFM
SRAM
SRAM
SRAM
(Core Logic)
(Core Logic)
(Core Logic)
I/Os Drive Out
According to Design
I/Os Clamped to
Specified States
I/Os Drive Out
According to New Design
Using ISP Clamp in the Quartus II Software
You have to define the states of the I/O pins to use the ISP clamp feature. There are
two ways to define the pin states in the Quartus II software. You can either:
■
Use an I/O Pin State file (.ips), or
■
Use the Assignment Editor to set the clamp states of the pins
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
