11–10
Chapter 11: In-System Programmability Guidelines for MAX II Devices
ISP via In-Circuit Testers
Porting the Jam Player
The Altera Jam Player (both Byte-Code and ASCII versions) works with a PC parallel
port. To port the Jam Player to your processor, you only need to modify the jamstub.c
or jbistub.c file (for the ASCII Jam Player or Jam Byte-Code Player, respectively). All
other files should remain the same. If the Jam Player is ported incorrectly, an
Unrecognized Device error is generated. The most common causes for this error are
listed below:
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After porting the Jam Player, the TDOvalue may be read in reversed polarity. This
problem may occur because the default I/O code in the Jam Player assumes the
use of the PC parallel port.
■
Although the TMSand TDIsignals are clocked in on the rising edge of TCK,
outputs do not change until the falling edge of TCK. This situation causes a half
TCKclock cycle lag in reading out the values. If the TDOtransition is expected on
the rising edge, the data appears to be offset by one clock.
■
Altera recommends using registers to synchronize the output transitions. In
addition, some processor data ports use a register to synchronize the output
signals. For example, reading and writing to the PC’s parallel port is accomplished
by reading and writing to registers. The use of these registers must be taken into
consideration when reading and writing to the JTAG chain. Incorrect accounting
of these registers can cause the values to either lead or lag the expected value.
ISP via In-Circuit Testers
MAX II devices can also be in-system programmed via in-circuit testers. For more
information about using Agilent’s 3070 in-circuit tester to in-system program MAX II
devices, refer to the Using Jam STAPL for ISP via an Embedded Processor chapter in the
MAX II Device Handbook.
Conclusion
The information provided in this document is based on development experiences and
customer issues resolved by Altera. For more information about resolving in-system
programming problems, contact Altera Applications.
Referenced Documents
This chapter references the following documents:
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■
■
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AN 75: High-Speed Board Designs
ByteBlasterMV Download Cable User Guide
ByteBlaster II Download Cable User Guide
DC and Switching Characteristics chapter in the MAX II Device Handbook
IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices chapter in the MAX II
Device Handbook
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■
JTAG and In-System Programmability chapter in the MAX II Device Handbook
MasterBlaster Serial/USB Communications Cable User Guide
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
