欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM240T100C5 参数 Datasheet PDF下载

EPM240T100C5图片预览
型号: EPM240T100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [最大II器件]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPM240T100C5的Datasheet PDF文件第195页浏览型号EPM240T100C5的Datasheet PDF文件第196页浏览型号EPM240T100C5的Datasheet PDF文件第197页浏览型号EPM240T100C5的Datasheet PDF文件第198页浏览型号EPM240T100C5的Datasheet PDF文件第200页浏览型号EPM240T100C5的Datasheet PDF文件第201页浏览型号EPM240T100C5的Datasheet PDF文件第202页浏览型号EPM240T100C5的Datasheet PDF文件第203页  
Chapter 11: In-System Programmability Guidelines for MAX II Devices  
11–5  
IEEE Std. 1149.1 Signals  
Further, because the TCKsignal must drive all IEEE Std. 1149.1 devices in the chain in  
parallel, the signal may have a high fan-out. Like any other high fan-out user-mode  
clock, you must manage a clock tree to maintain signal integrity. Typical errors that  
result from clock integrity problems are invalid ID messages, blank-check errors, or  
verification errors.  
Altera recommends pulling the TCKsignal low through the internal weak pull-down  
resistor or an external 1-kΩ resistor.  
Fast TCKedges combined with board inductance can cause overshoot problems.  
When this combination occurs, you must either reduce inductance on the trace or  
reduce the switching rate by selecting a transistor-to-transistor logic (TTL) driver chip  
with a slower slew rate. Altera does not recommend using resistor and capacitor (RC)  
networks to slow down edge rates, because they can violate the device’s input  
specifications. In most cases, using a driver chip prevents the edge rate from being too  
slow. Altera recommends using driver chips that do not glitch upon power-up.  
Programming via a Download Cable  
TM  
TM  
You can program MAX II devices using a MasterBlaster , ByteBlasterMV  
,
TM  
ByteBlaster II, or USB Blaster download cable. Using a PC or UNIX workstation  
with the Quartus II software programmer, Programmer Object File (.pof), JamTM  
Files (.jam), or Jam Byte-Code Files (.jbc) can be downloaded to the MAX II devices  
via the download cable.  
If you are using the download cables and your JTAG chain contains three or more  
devices, Altera recommends adding a buffer to the chain. You should select a buffer  
with slow transitions to minimize noise, but be sure that the transition rates can still  
meet TCKperformance requirements of your chain.  
If you must extend the download cable, you can attach a standard PC parallel or USB  
port cable to the download cable. Do not extend the 10-pin header portion of the  
download cable; extending this portion of the cable can cause noise and in-system  
programming problems.  
f
Different download cables will have different programming times. For more  
information about the MasterBlaster, ByteBlasterMV, ByteBlaster II, or USB Blaster  
download cable, refer to the MasterBlaster Serial/USB Communications Cable User Guide,  
ByteBlasterMV Download Cable User Guide, ByteBlaster II Download Cable User Guide, or  
USB-Blaster Download Cable User Guide.  
Disabling IEEE Std. 1149.1 Circuitry  
By default, the JTAG circuitry in MAX II devices is always enabled because they have  
dedicated JTAG pins and circuitry. The JTAG circuitry must be enabled during ISP  
and boundary-scan testing, but disabled at all other times. If your design does not use  
ISP or boundary-scan test (BST) circuitry, Altera recommends disabling the IEEE Std.  
1149.1 circuitry.  
To disable the JTAG circuitry, Altera recommends pulling TMShigh and TCKlow.  
Pulling TCKlow ensures that a rising edge does not occur on TCKduring the power-  
up sequence. You can pull TCKhigh, but you must first pull TMShigh. Pulling TMS  
high first ensures that the rising edge or edges on TCKdo not cause the JTAG state  
machine to leave the test-logic-reset state.  
© October 2008 Altera Corporation  
MAX II Device Handbook