Chapter 11: In-System Programmability Guidelines for MAX II Devices
11–3
General ISP Guidelines
Interrupting In-System Programming
Altera does not recommend interrupting the programming process. However, the
MAX II device has an ISP_DONEbit that will only be set at the very end of a
successful program sequence. The I/O pins will only drive out if this bit is set. This
prevents a partially programmed device from driving out and operating
unpredictably.
MultiVolt Devices and Power-Up Sequences
For the JTAG circuitry to operate correctly during in-system programming or
boundary-scan testing, all devices in a JTAG chain must be in the same state.
Therefore, in systems with multiple power supply voltages, the JTAG pins must be
held in the test-logic-reset state until all devices in the chain are completely powered
up. This procedure is particularly important because systems with multiple power
supplies cannot power all voltage levels simultaneously.
MAX II devices have the MultiVolt feature and can use more than one power supply
voltage: VCCINT and VCCIO for each I/O bank. VCCINT provides power to the JTAG
circuitry; VCCIO provides power to input pins and output drivers for output pins,
including TDO. Therefore, when using two power supply voltages, the JTAG circuitry
must be held in the test-logic-reset state until both power supplies are turned on. If the
JTAG pins are not held in the test-logic-reset state, in-system programming errors can
occur.
VCCIO Powered before VCCINT
If VCCIO is powered up before VCCINT, the JTAG circuitry is not active but TDOis tri-
stated. Even though the JTAG circuitry is not active, if the next device in the JTAG
chain is powered up with the same trace as VCCIO, its JTAG circuitry must stay in the
test-logic-reset state. Because all TMSand TCKsignals are common, they must be
disabled for all devices in the chain. Therefore, the JTAG pins must be disabled by
pulling TCKlow and TMShigh.
I/O Pins Tri-Stated during In-System Programming
By default, all device I/O pins are tri-stated during in-system programming. In
addition, the MAX II device provides a weak pull-up resistor during ISP. The purpose
of this weak pull-up resistor is to eliminate the need for external pull-up resistors on
tri-stated I/O pins.
For pins that are used to drive signals and require a particular value during in-system
programming (for example, output enable or chip enable signals), you can use the in-
system programming clamp feature or the real-time ISP feature available for MAX II
devices. These two features ensure that each I/O pin is clamped to a specific state
during in-system programming.
f
For more information, refer to the In-System Programming Clamp and Real-Time ISP
sections in the JTAG and In-System Programmability chapter in the MAX II Device
Handbook.
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
