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EPM240T100C5N 参数 Datasheet PDF下载

EPM240T100C5N图片预览
型号: EPM240T100C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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13–16
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
Disabling IEEE Std. 1149.1 BST Circuitry
Disabling IEEE Std. 1149.1 BST Circuitry
The IEEE Std. 1149.1 BST circuitry for MAX II devices is enabled upon device power-
up. Because this circuitry may be used for BST or ISP, this circuitry must be enabled
only if these features are used. This section describes how to disable the IEEE Std.
1149.1 circuitry to ensure that the circuitry is not inadvertently enabled when it is not
needed.
shows the pin connections necessary for disabling JTAG in MAX II devices
that have dedicated IEEE Std. 1149.1 pins.
Table 13–3.
Disabling IEEE Std. 1149.1 Circuitry
JTAG Pins
TMS
VCC
Notes to
(1) There is no software option to disable JTAG in MAX II devices. The JTAG pins are dedicated.
(2)
VCC
refers to V
CCIO
of Bank 1.
(3) The
TCK
signal may also be tied high. If TCK is tied high, power-up conditions must ensure that
TMS
is pulled
high before
TCK.
Pulling
TCK
low avoids this power-up condition.
TCK
GND
TDI
VCC
TDO
Leave Open
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
Use the following guidelines when performing boundary-scan testing with IEEE Std.
1149.1 devices:
If a pattern (for example, a 10-bit
1010101010
pattern) does not shift out of the
instruction register via the
TDO
pin during the first clock cycle of the
SHIFT_IR
state, the proper TAP controller state has not been reached. To solve this problem,
try one of the following procedures:
Verify that the TAP controller has reached the
SHIFT_IR
state correctly. To
advance the TAP controller to the
SHIFT_IR
state, return to the
RESET
state
and clock the code
01100
on the TMS pin.
Check the connections to the
VCC,
GND, and JTAG pins on the device.
Perform a
SAMPLE/PRELOAD
test cycle prior to the first
EXTEST
test cycle to
ensure that known data is present at the device pins when the
EXTEST
mode is
entered. If the
OEJ
update register contains a 0, the data in the
OUTJ
update
register will be driven out. The state must be known and correct to avoid
contention with other devices in the system.
Do not perform
EXTEST
and
SAMPLE/PRELOAD
tests during ISP. These
instructions are supported before and after ISP but not during ISP.
1
If problems persist, contact Altera Applications.