14–2
Chapter 14: Using Jam STAPL for ISP via an Embedded Processor
Embedded Systems
Figure 14–1.
Embedded System Block Diagram
Embedded System
Download Cable
TDI
TMS
TCK
TDO
TDI
Control
8
4
20
adr[19..0]
Control
TMS
TDI
TCK
d[3..0]
TDO
TMS
TCK
TDO
Interface
Logic
(Optional)
d[7..0]
Any JTAG
Device
Embedded
Processor
TDI
Control
8
20
20
d[7..0]
adr[19..0]
EPROM or
System
Memory
TMS
TCK
TDO
MAX II Devices
adr[19..0]
TDI
TMS
TCK
TDO
Any JTAG
Device
Both JTAG connection methods should include space for the MasterBlaster™,
ByteBlaster™ II, or USB-Blaster™ header connection. The header is useful during
prototyping because it allows designers to quickly verify or modify the PLD’s
contents. During production, the header can be removed to decrease cost.
Example Interface PLD Design
shows an example design schematic of an interface PLD. A different
design can be implemented; however, important points exemplified in this design are:
■
■
TMS, TCK,
and
TDI
should be synchronous outputs
Multiplexer logic should be included to allow board access for the MasterBlaster,
ByteBlaster II, or USB-Blaster download cable
1
This design example is for reference only. All of the inputs except
data[3..0]
are
optional and included only to show how an interface PLD can act as an address
decoder on an embedded data bus.
ALTERA [ ALTERA CORPORATION ]
