13–4
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
IEEE Std. 1149.1 Boundary-Scan Register
shows how test data is serially shifted around the periphery of the IEEE
Std. 1149.1 device.
Figure 13–3.
Boundary-Scan Register
Internal Logic
Each peripheral
element is either an
I/O pin, dedicated
input pin, or
dedicated
configuration pin.
TAP Controller
TDI
TMS
TCK
TDO
Boundary-Scan Cells of a MAX II Device I/O Pin
Except for the four JTAG pins and power pins, all pins of a MAX II device (including
clock pins) can be used as user I/O pins and have a boundary-scan cell (BSC). The 3-
bit BSC consists of a set of capture registers and a set of update registers. The capture
registers can connect to internal device data via the
OUTJ
and
OEJ
signals, while the
update registers connect to external data through the
PIN_OUT
and
PIN_OE
signals.
The global control signals for the IEEE Std. 1149.1 BST registers (for example,
SHIFT,
CLOCK,
and
UPDATE)
are generated internally by the TAP controller; the
MODE
signal
is generated by a decode of the instruction register. The data signal path for the
boundary-scan register runs from the serial data in (SDI) signal to the serial data out
(SDO) signal. The scan register begins at the
TDI
pin and ends at the
TDO
pin of the
device.
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