Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
IEEE Std. 1149.1 Boundary-Scan Register
13–3
shows a functional model of the IEEE Std. 1149.1 circuitry.
Figure 13–2.
IEEE Std. 1149.1 Circuitry
Instruction Register
TDI
UPDATEIR
CLOCKIR
SHIFTIR
TDO
TMS
TCK
TAP
Controller
UPDATEDR
CLOCKDR
SHIFTDR
Instruction Decode
Data Registers
Bypass Register
Boundary-Scan Register
(1)
a
Device ID Register
ISP Registers
Note to
(1)
Refer to the
chapter in the
MAX II Device Handbook
for the boundary-scan register length in MAX II devices.
IEEE Std. 1149.1 boundary-scan testing is controlled by a TAP controller, which is
described in
The
TMS
and
TCK
pins operate the TAP controller, and the
TDI
and
TDO
pins provide the serial path
for the data registers. The
TDI
pin also provides data to the instruction register, which
then generates control logic for the data registers.
IEEE Std. 1149.1 Boundary-Scan Register
The boundary-scan register is a large serial shift register that uses the
TDI
pin as an
input and the
TDO
pin as an output. The boundary-scan register consists of 3-bit
peripheral elements that are associated with I/O pins of the MAX II devices. You can
use the boundary-scan register to test external pin connections or to capture internal
data.
f
Refer to
the
chapter in the
MAX II Device Handbook
for the boundary-scan register length of MAX II devices.
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