13. IEEE 1149.1 (JTAG) Boundary-Scan
Testing for MAX II Devices
MII51014-1.7
Introduction
As printed circuit boards (PCBs) become more complex, the need for thorough testing
becomes increasingly important. Advances in surface-mount packaging and PCB
manufacturing have resulted in smaller boards, making traditional test methods (for
example, external test probes and “bed-of-nails” test fixtures) harder to implement.
As a result, cost savings from PCB space reductions are sometimes offset by cost
increases in traditional testing methods.
In the 1980s, the Joint Test Action Group (JTAG) developed a specification for
boundary-scan testing that was later standardized as the IEEE Std. 1149.1
specification. This boundary-scan test (BST) architecture offers the capability to
efficiently test components on PCBs with tight lead spacing.
This BST architecture can test pin connections without using physical test probes and
capture functional data while a device is operating normally. Boundary-scan cells in a
device can force signals onto pins, or capture data from pin or core logic signals.
Forced test data is serially shifted into the boundary-scan cells. Captured data is
serially shifted out and externally compared to expected results.
shows
the concept of boundary-scan testing.
Figure 13–1.
IEEE Std. 1149.1 Boundary-Scan Testing
Boundary-Scan Cell
Serial
Data In
IC
Pin Signal
Serial
Data Out
Core
Logic
Core
Logic
Interconnection
to Be Tested
JTAG Device 1
JTAG Device 2
This chapter discusses how to use the IEEE Std. 1149.1 BST circuitry in MAX
®
II
devices. The topics are as follows:
■
■
■
■
■
■
■
■
ALTERA [ ALTERA CORPORATION ]
