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EPM240T100C5N 参数 Datasheet PDF下载

EPM240T100C5N图片预览
型号: EPM240T100C5N
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分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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13–2
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
IEEE Std. 1149.1 BST Architecture
In addition to BST, you can use the IEEE Std. 1149.1 controller for in-system
programming for MAX II devices. MAX II devices support IEEE 1532 programming,
which utilizes the IEEE Std. 1149.1 Test Access Port (TAP) interface. However, this
chapter only discusses the BST feature of the IEEE Std. 1149.1 circuitry.
IEEE Std. 1149.1 BST Architecture
A MAX II device operating in IEEE Std. 1149.1 BST mode uses four required pins,
TDI, TDO, TMS,
and
TCK.
summarizes the functions of each of these pins.
MAX II devices do not have a
TRST
pin.
Table 13–1.
EEE Std. 1149.1 Pin Descriptions
Pin
TDI
TDO
Description
Test data input
Test data output
Function
Serial input pin for instructions as well as test and
programming data. Data is shifted in on the rising edge of
TCK.
Serial data output pin for instructions as well as test and
programming data. Data is shifted out on the falling edge of
TCK.
The pin is tri-stated if data is not being shifted out of the
device.
Input pin that provides the control signal to determine the
transitions of the TAP controller state machine. Transitions
within the state machine occur at the rising edge of
TCK.
Therefore,
TMS
must be set up before the rising edge of
TCK.
TMS
is evaluated on the rising edge of
TCK.
The clock input to the BST circuitry. Some operations occur at
the rising edge, while others occur at the falling edge.
TMS
Test mode select
TCK
Test clock input
Notes to
(1) The
TDI
and
TMS
pins have internal weak pull-up resistors.
(2) The
TCK
pin has an internal weak pull-down resistor.
The IEEE Std. 1149.1 BST circuitry requires the following registers:
The instruction register, which is used to determine the action to be performed and
the data register to be accessed.
The bypass register, which is a 1-bit-long data register used to provide a
minimum-length serial path between
TDI
and
TDO.
The boundary-scan register that is a shift register composed of all the boundary-
scan cells of the device.