FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
The Up/down counter mode uses 2 three-input LUTs: one generates the
counter data, and the other generates the fast carry bit. A 2-to-1
multiplexer provides synchronous loading. Data can also be loaded
asynchronously with the clear and preset register control signals, without
using the LUT resources.
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Clearable counter mode uses 2 three-input LUTs: one generates the
counter data, and the other generates the fast carry bit. Synchronous
loading is provided by a 2-to-1 multiplexer. The output of this multiplexer
is ANDed with a synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-stating without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OEsignals are active, contending signals can be
driven onto the bus. Conversely, if no OEsignals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1or LABCTRL2can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1is asserted, DATA3is loaded into the
register.
Altera Corporation
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