FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load,
or with an asynchronous clear. If DATA3is tied to VCC, asserting
LABCTRL1asynchronously loads a one into the register. Alternatively, the
Altera software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRLsignals, the DATA3input is not
needed and can be used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1controls
the preset and LABCTRL2controls the clear. DATA3is tied to VCC
,
therefore, asserting LABCTRL1asynchronously loads a one into the
register, effectively presetting the register. Asserting LABCTRL2clears the
register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1implements the asynchronous load of DATA3by controlling
the register preset and clear. LABCTRL2implements the clear by
controlling the register clear; LABCTRL2does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2presets the
register, while asserting LABCTRL1loads the register. The Altera software
inverts the signal that drives DATA3to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1implements the asynchronous load of DATA3by controlling
the register preset and clear.
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Altera Corporation
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