FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 10. LE Clear & Preset Modes
Asynchronous Clear
Asynchronous Preset
Asynchronous Clear & Preset
labctrl1
VCC
Chip-Wide Reset
labctrl1 or
PRN
PRN
D
Q
labctrl2
D
Q
PRN
D
Q
CLRN
CLRN
labctrl1 or
labctrl2
labctrl2
Chip-Wide Reset
CLRN
Chip-Wide Reset
VCC
Asynchronous Load without Clear or Preset
Asynchronous Load with Clear
NOT
NOT
labctrl1
(Asynchronous
Load)
labctrl1
(Asynchronous
Load)
PRN
PRN
data3
(Data)
D
Q
data3
(Data)
D
Q
NOT
CLRN
CLRN
labctrl2
(Clear)
NOT
Chip-Wide Reset
Chip-WideReset
Asynchronous Load with Preset
NOT
labctrl1
(Asynchronous
Load)
labctrl2
(Preset)
PRN
D
Q
data3
(Data)
CLRN
NOT
Chip-Wide Reset
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1or LABCTRL2. In this
mode, the preset signal is tied to VCC to deactivate it.
Altera Corporation
23
ALTERA [ ALTERA CORPORATION ]
