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EPF10K30RC208-3 参数 Datasheet PDF下载

EPF10K30RC208-3图片预览
型号: EPF10K30RC208-3
PDF下载: 下载PDF文件 查看货源
内容描述: 嵌入式可编程逻辑器件系列 [Embedded Programmable Logic Device Family]
分类和应用: 可编程逻辑器件输入元件LTE时钟
文件页数/大小: 128 页 / 1975 K
品牌: ALTERA [ ALTERA CORPORATION ]
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FLEX 10K Embedded Programmable Logic Device Family Data Sheet  
Normal Mode  
The normal mode is suitable for general logic applications and wide  
decoding functions that can take advantage of a cascade chain. In normal  
mode, four data inputs from the LAB local interconnect and the carry-in  
are inputs to a four-input LUT. The Compiler automatically selects the  
carry-in or the DATA3signal as one of the inputs to the LUT. The LUT  
output can be combined with the cascade-in signal to form a cascade chain  
through the cascade-out signal. Either the register or the LUT can be used  
to drive both the local interconnect and the FastTrack Interconnect at the  
same time.  
The LUT and the register in the LE can be used independently; this feature  
is known as register packing. To support register packing, the LE has two  
outputs; one drives the local interconnect and the other drives the  
FastTrack Interconnect. The DATA4signal can drive the register directly,  
allowing the LUT to compute a function that is independent of the  
registered signal; a three-input function can be computed in the LUT, and  
a fourth independent signal can be registered. Alternatively, a four-input  
function can be generated, and one of the inputs to this function can be  
used to drive the register. The register in a packed LE can still use the clock  
enable, clear, and preset signals in the LE. In a packed LE, the register can  
drive the FastTrack Interconnect while the LUT drives the local  
interconnect, or vice versa.  
Arithmetic Mode  
The arithmetic mode offers 2 three-input LUTs that are ideal for  
implementing adders, accumulators, and comparators. One LUT  
computes a three-input function, and the other generates a carry output.  
As shown in Figure 9 on page 19, the first LUT uses the carry-in signal and  
two data inputs from the LAB local interconnect to generate a  
combinatorial or registered output. For example, in an adder, this output  
is the sum of three signals: a, b, and carry-in. The second LUT uses the  
same three signals to generate a carry-out signal, thereby creating a carry  
chain. The arithmetic mode also supports simultaneous use of the cascade  
chain.  
20  
Altera Corporation  
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