Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Figure 4–18 shows the timing waveform for FPGA AS configuration
scheme using a serial configuration device.
Figure 4–18. AS Configuration Timing
t
POR
nCONFIG
nSTATUS
CONF_DONE
nCSO
t
CL
DCLK
t
CH
t
H
Read Address
ASDO
t
SU
DATA0
bit N
bit N − 1
bit 1
bit 0
136 Cycles
INIT_DONE
User I/O
User Mode
Table 4–14 shows the timing parameters for AS configuration mode.
Table 4–14. Timing Parameters for AS Configuration
Symbol
Parameter
Min
Typ
Max
Unit
fCLK
14
20 (2)
10
17
26 (2)
13
20
40 (2)
20
MHz
MHz
MHz
ns
DCLKfrequency from Cyclone FPGA
fCLK
DCLKfrequency from Stratix II or Cyclone II FPGA
(1)
tCH
tCL
tH
25
DCLKhigh time
25
ns
DCLKlow time
0
ns
Data hold time after rising edge on DCLK
Data set up time before rising edge on DCLK
POR delay
tSU
tPOR
5
ns
100
ms
Notes to Table 4–14:
(1) These values are preliminary
(2) Only the EPCS16 and EPCS64 devices support a DCLKfrequency up to 40 MHz.
Altera Corporation
July 2004
Core Version a.b.c variable
4–27
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
