Timing Information
parameter specifies the VCC supply current when the device is in active
power mode and the ICC0 parameter specifies the current when the device
is in stand-by power mode (see Table 4–18).
Power-On Reset
During initial power-up, a POR delay occurs to ensure the system voltage
levels have stabilized. During AS configuration, the FPGA controls the
configuration and has a longer POR delay than the serial configuration
device. Therefore, the POR delay is governed by the Stratix II FPGA
(typically 12 ms or 100 ms) or Cyclone series FPGA (typically 100 ms).
Error Detection
During AS configuration with the serial configuration device, the FPGA
monitors the configuration status through the nSTATUSand CONF_DONE
pins. If an error condition occurs (nSTATUSdrives low) or if the
CONF_DONEpin does not go high, the FPGA will initiate reconfiguration
by pulsing the nSTATUSand nCSOsignals, which controls the chip select
pin on the serial configuration device (nCS).
After an error, configuration automatically restarts if the Auto-Restart
Upon Frame Error option is turned on in the Quartus II software. If the
option is turned off, the system must monitor the nSTATUSsignal for
errors and then pulse the nCONFIGsignal low to restart configuration.
Figure 4–16 shows the timing waveform for write operation to the serial
configuration device.
Timing
Information
Figure 4–16. Write Operation Timing
t
CSH
nCS
t
t
t
t
CL
NCSH
NCSSU
CH
DCLK
ASDI
DATA
t
t
DH
DSU
Bit n
Bit n
1
Bit 0
High Impedance
4–24
Configuration Handbook, Volume 2
Core Version a.b.c variable
Altera Corporation
July 2004
ALTERA [ ALTERA CORPORATION ]
