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EPCS4SI8N 参数 Datasheet PDF下载

EPCS4SI8N图片预览
型号: EPCS4SI8N
PDF下载: 下载PDF文件 查看货源
内容描述: 串行配置器件 [Serial Configuration Devices]
分类和应用: 存储内存集成电路光电二极管过程控制系统PCSLTE可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 32 页 / 241 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet  
The erase sector operation is implemented by first driving nCSlow, then  
shifting in the erase sector operation code and the three address bytes of  
the chosen sector on the ASDIpin. The three address bytes for the erase  
sector operation can be any address inside the specified sector. (See  
Tables 4–6 and 4–7 for sector address range information.) Drive nCShigh  
after the eighth bit of the erase sector operation code has been latched in.  
Figure 4–15 shows the timing diagram.  
Immediately after the device drives nCShigh, the self-timed erase sector  
cycle is initiated. The self-timed erase sector cycle usually takes 2 s for  
EPCS1 and EPCS4 devices and is guaranteed to be less than 3 s for both  
serial configuration devices. You must account for this amount of delay  
before the memory contents can be accessed. Alternatively, you can check  
the write in progress bit in the status register by executing the read status  
operation while the erase cycle is in progress. The write in progress bit is  
1during the self-timed erase cycle and is 0when it is complete. The write  
enable latch bit in the status register is reset to 0before the erase cycle is  
complete.  
Figure 4–15. Erase Sector Operation Timing Diagram  
nCS  
DCLK  
ASDI  
0
1
2
3
4
5
6
7
8
9
28 29 30 31  
Operation Code  
24-Bit Address  
23 22  
3
2
1
0
MSB  
This section describes the power modes, power-on reset (POR) delay,  
error detection, and initial programming state of serial configuration  
devices.  
Power &  
Operation  
Power Mode  
Serial configuration devices support active power and standby power  
modes. When nCSis low, the device is enabled and is in active power  
mode. The FPGA is configured while in active power mode. When nCSis  
high, the device is disabled but could remain in active power mode until  
all internal cycles have completed (such as write or erase operations). The  
serial configuration device then goes into stand-by power mode. The ICC1  
Altera Corporation  
July 2004  
Core Version a.b.c variable  
4–23  
Configuration Handbook, Volume 2  
 
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